Magnetoelectronics, spin electronics and spintronics are synonymous terms for the use of effects predominantly caused by electron spin. Magnetoelectronics is used in numerous information devices, and provides non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. The numerous magnetoelectronics information devices include, but are not limited to MRAM.
MRAM is generally composed of magnetoresistive memory cells, word lines, and bit lines intersecting the word lines. The memory cells are typically formed with a Magnetic Tunnel Junction (MTJ). In addition, each of the memory cells is typically formed with an isolation or select device that is configured to electrically isolate the memory cell from other memory cells when reading the magnetization state or value of the memory cell. For example, each of the memory cells is typically formed with an isolation transistor, such as a Metal Oxide Field Effect Transistor (MOSFET), which can be configured to electrically isolate the memory cell from other memory cells in the memory. Utilization of an isolation device, such as an isolation transistor, in each memory cell limits the cell density, and MRAMs with increased cell densities are continually sought. Accordingly, it is desirable to reduce the limits in MRAM cell density imposed with an isolation or select device in each memory cell, such as an isolation transistor in each memory cell.
In view of the foregoing, it is desirable to provide an MRAM having one or more memory cells that are formed without an isolation device, such as an isolation transistor. In addition, it is desirable to provide an MRAM with memory cells that only include an MTJ. Furthermore, it is desirable to provide methods for reading an MTJ in an MRAM. It is also desirable to improve the memory array efficiency, a metric that measures the amount of area devoted to the memory, which is compared to the overall die or circuit size that includes peripheral circuitry used to perform addressing, reading, interfacing to other logic circuits either on chip or off-chip. For example, the array efficiency of FLASH memory has been decreasing as a result of supply voltage scaling while charge pump circuitry requirements are inversely scaling with supply voltage. Moreover, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.